Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito 0005, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada. A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. J. Solid-State Circuits, 34(11):1619-1626, 1999. [doi]
@article{KubosawaHATAASS99,
title = {A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism},
author = {Hajime Kubosawa and Naoshi Higaki and Satoshi Ando and Hiromasa Takahashi and Yoshimi Asada and Hideaki Anbutsu and Tomio Sato and Masato Sakate and Atsuhiro Suga and Michihide Kimura and Hideo Miyake and Hiroshi Okano and Akira Asato and Yasunori Kimura and Hiroshi Nakayama and Masayoshi Kimoto and Katsuji Hirochi and Hideki Saito 0005 and Norio Kaido and Yukihiro Nakagawa and Toshio Shimada},
year = {1999},
doi = {10.1109/4.799871},
url = {https://doi.org/10.1109/4.799871},
researchr = {https://researchr.org/publication/KubosawaHATAASS99},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {34},
number = {11},
pages = {1619-1626},
}