Minimizing clock domain crossing in Network on Chip interconnect - researchr publication related

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Parag Kulkarni, Puneet Gupta, Rudy Beraha. Minimizing clock domain crossing in Network on Chip interconnect. In Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014. pages 292-299, IEEE, 2014. [doi]

The following publications are possibly variants of this publication:

Testing of Clock-Domain Crossing Faults in Multi-core System-on-ChipNaghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil. ats 2011: 7-14 [doi]

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