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Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula. Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. IEEE Trans. VLSI Syst., 24(9):2873-2886, 2016. [doi]

Authors

Niranjan Kulkarni

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Jinghua Yang

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Jae-sun Seo

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Sarma B. K. Vrudhula

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