Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula. Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. IEEE Trans. VLSI Syst., 24(9):2873-2886, 2016. [doi]
@article{KulkarniYSV16,
title = {Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops},
author = {Niranjan Kulkarni and Jinghua Yang and Jae-sun Seo and Sarma B. K. Vrudhula},
year = {2016},
doi = {10.1109/TVLSI.2016.2527783},
url = {http://dx.doi.org/10.1109/TVLSI.2016.2527783},
researchr = {https://researchr.org/publication/KulkarniYSV16},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {24},
number = {9},
pages = {2873-2886},
}