Formal Probabilistic Timing Verification in RTL

Jayanand Asok Kumar, Shobha Vasudevan. Formal Probabilistic Timing Verification in RTL. IEEE Trans. on CAD of Integrated Circuits and Systems, 32(5):788-801, 2013. [doi]

Authors

Jayanand Asok Kumar

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Shobha Vasudevan

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