A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang. A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014. pages 1-4, IEEE, 2014. [doi]

This author has not been identified. Look up 'Ming-Zhang Kuo' in GoogleThis author has not been identified. Look up 'Henry Hsieh' in GoogleThis author has not been identified. Look up 'Sang H. Dhong' in GoogleThis author has not been identified. Look up 'Ping-Lin Yang' in GoogleThis author has not been identified. Look up 'Cheng-Chung Lin' in GoogleThis author has not been identified. Look up 'Ryan Tseng' in GoogleThis author has not been identified. Look up 'Kevin Huang' in GoogleThis author has not been identified. Look up 'Min-Jer Wang' in GoogleThis author has not been identified. Look up 'Wei Hwang' in Google

runs on WebDSL