Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang. A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014. pages 1-4, IEEE, 2014. [doi]
@inproceedings{KuoHDYLTHWH14,
title = {A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS},
author = {Ming-Zhang Kuo and Henry Hsieh and Sang H. Dhong and Ping-Lin Yang and Cheng-Chung Lin and Ryan Tseng and Kevin Huang and Min-Jer Wang and Wei Hwang},
year = {2014},
doi = {10.1109/CICC.2014.6946030},
url = {http://dx.doi.org/10.1109/CICC.2014.6946030},
researchr = {https://researchr.org/publication/KuoHDYLTHWH14},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014},
publisher = {IEEE},
}