A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector

Dae Hyun Kwon, Minkyu Kim, Sung-Geun Kim, Woo-Young Choi. A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector. IEEE Trans. on Circuits and Systems, 66(2):362-366, 2019. [doi]

Authors

Dae Hyun Kwon

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Minkyu Kim

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Sung-Geun Kim

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Woo-Young Choi

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