Dae Hyun Kwon, Minkyu Kim, Sung-Geun Kim, Woo-Young Choi. A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector. IEEE Trans. on Circuits and Systems, 66(2):362-366, 2019. [doi]
@article{KwonKKC19,
title = {A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector},
author = {Dae Hyun Kwon and Minkyu Kim and Sung-Geun Kim and Woo-Young Choi},
year = {2019},
doi = {10.1109/TCSII.2018.2855692},
url = {https://doi.org/10.1109/TCSII.2018.2855692},
researchr = {https://researchr.org/publication/KwonKKC19},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {66},
number = {2},
pages = {362-366},
}