Kanishka Lahiri, Anand Raghunathan, Sujit Dey. Design space exploration for optimizing on-chip communication architectures. IEEE Trans. on CAD of Integrated Circuits and Systems, 23(6):952-961, 2004. [doi]
@article{LahiriRD04a,
title = {Design space exploration for optimizing on-chip communication architectures},
author = {Kanishka Lahiri and Anand Raghunathan and Sujit Dey},
year = {2004},
doi = {10.1109/TCAD.2004.828127},
url = {http://doi.ieeecomputersociety.org/10.1109/TCAD.2004.828127},
tags = {optimization, architecture, design},
researchr = {https://researchr.org/publication/LahiriRD04a},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {23},
number = {6},
pages = {952-961},
}