Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana. The LOTTERYBUS on-chip communication architecture. IEEE Trans. VLSI Syst., 14(6):596-608, 2006. [doi]
@article{LahiriRL06,
title = {The LOTTERYBUS on-chip communication architecture},
author = {Kanishka Lahiri and Anand Raghunathan and Ganesh Lakshminarayana},
year = {2006},
doi = {10.1109/TVLSI.2006.878210},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2006.878210},
tags = {architecture},
researchr = {https://researchr.org/publication/LahiriRL06},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {14},
number = {6},
pages = {596-608},
}