Yi-Hao Lan, Shen-Iuan Liu. A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector. IEEE Trans. VLSI Syst., 32(4):704-713, April 2024. [doi]
@article{LanL24-0,
title = {A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector},
author = {Yi-Hao Lan and Shen-Iuan Liu},
year = {2024},
month = {April},
doi = {10.1109/TVLSI.2023.3330012},
url = {https://doi.org/10.1109/TVLSI.2023.3330012},
researchr = {https://researchr.org/publication/LanL24-0},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {32},
number = {4},
pages = {704-713},
}