The following publications are possibly variants of this publication:
- From Parallelism Levels to a Multi-ASIP Architecture for Turbo DecodingOlivier Muller, Amer Baghdadi, Michel Jézéquel. tvlsi, 17(1):92-102, 2009. [doi]
- A flexible high throughput multi-ASIP architecture for LDPC and turbo decodingPurushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel. date 2011: 228-233 [doi]
- On chip interconnects for multiprocessor turbo decoding architecturesMaurizio Martina, Guido Masera, Hazem Moussa, Amer Baghdadi. mam, 35(2):167-181, 2011. [doi]
- Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decodingVianney Lapotre, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet. ejasp, 2017:35, 2017. [doi]
- Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo DecoderVianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet. dsd 2013: 155-162 [doi]
- A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo DecodingVianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet. tvlsi, 24(1):383-387, 2016. [doi]
- A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP contextVianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner. isvlsi 2013: 40-45 [doi]