An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications - researchr publication related

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Van Loi Le, Juhui Li, Alan Chang, Tony T. Kim. An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. pages 197-200, IEEE, 2017. [doi]

The following publications are possibly variants of this publication:

A novel CMOS double-edge triggered flip-flop for low-power applicationsYu-Yin Sung, Robert C. Chang. iscas 2004: 665-668

Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOSDavid Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong. cicc 2011: 1-4 [doi]

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