A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation

Joon-Yeong Lee, Kwangseok Han, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Taehun Yoon, Jinho Park, Hyeon-Min Bae. A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation. In 2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015. pages 1-4, IEEE, 2015. [doi]

@inproceedings{LeeHKLLYPB15,
  title = {A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation},
  author = {Joon-Yeong Lee and Kwangseok Han and Taeho Kim and Sangeun Lee and Jeong-Sup Lee and Taehun Yoon and Jinho Park and Hyeon-Min Bae},
  year = {2015},
  doi = {10.1109/CICC.2015.7338372},
  url = {http://dx.doi.org/10.1109/CICC.2015.7338372},
  researchr = {https://researchr.org/publication/LeeHKLLYPB15},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015},
  publisher = {IEEE},
  isbn = {978-1-4799-8682-8},
}