The following publications are possibly variants of this publication:
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- A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOSKyongsu Lee, Youngjin Kim, Kyung-Sub Son, Sangmin Lee, Jin-Ku Kang. ieiceee, 11(17):20140671, 2014. [doi]
- A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOSWoo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog Kyoon Jeong. jssc, 51(10):2357-2367, 2016. [doi]