A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface - researchr publication authors

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Hyun-Woo Lee, Yong Hoon Kim, Won-Joo Yun, Eun-Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jong Ho Jung, Kyung-whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih. A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. pages 3861-3864, IEEE, 2010. [doi]

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