Hyun-Woo Lee, Yong Hoon Kim, Won-Joo Yun, Eun-Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jong Ho Jung, Kyung-whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih. A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. pages 3861-3864, IEEE, 2010. [doi]
@inproceedings{LeeKYPLKKJKRKCKCCK10,
title = {A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface},
author = {Hyun-Woo Lee and Yong Hoon Kim and Won-Joo Yun and Eun-Young Park and Kang Youl Lee and Jaeil Kim and Kwang Hyun Kim and Jong Ho Jung and Kyung-whan Kim and Nam Gyu Rye and Kwan-Weon Kim and Jun Hyun Chun and Chulwoo Kim and Young-Jung Choi and Byong-Tae Chung and Joong Sik Kih},
year = {2010},
doi = {10.1109/ISCAS.2010.5537703},
url = {http://dx.doi.org/10.1109/ISCAS.2010.5537703},
researchr = {https://researchr.org/publication/LeeKYPLKKJKRKCKCCK10},
cites = {0},
citedby = {0},
pages = {3861-3864},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France},
publisher = {IEEE},
}