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Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita. An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging. IEICE Transactions, 94-A(7):1519-1529, 2011. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debuggingYeonbok Lee, Takeshi Matsumoto, Masahiro Fujita. iccd 2010: 402-408 [doi] A Post-Silicon Debug Support Using High-Level Design DescriptionYeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita. ats 2009: 137-142 [doi] Utilizing high level design information to speed up post-silicon debuggingMasahiro Fujita. aspdac 2011: 301-305 [doi] A debugging method for repairing post-silicon bugs of high performance processors in the fieldsBijan Alizadeh, Masahiro Fujita. fpt 2010: 328-331 [doi] On-chip dynamic signal sequence slicing for efficient post-silicon debuggingYeonbok Lee, Takeshi Matsumoto, Masahiro Fujita. aspdac 2011: 719-724 [doi]
The following publications are possibly variants of this publication: