A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement - researchr publication authors

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Yu-Huei Lee, Shen-Yu Peng, Chao-Chang Chiu, Alex Chun-Hsien Wu, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee. A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement. J. Solid-State Circuits, 48(4):1018-1030, 2013. [doi]

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