Yu-Huei Lee, Shen-Yu Peng, Chao-Chang Chiu, Alex Chun-Hsien Wu, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee. A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement. J. Solid-State Circuits, 48(4):1018-1030, 2013. [doi]
@article{LeePCWCLWTHL13,
title = {A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement},
author = {Yu-Huei Lee and Shen-Yu Peng and Chao-Chang Chiu and Alex Chun-Hsien Wu and Ke-Horng Chen and Ying-Hsi Lin and Shih-Wei Wang and Tsung-Yen Tsai and Chen-Chih Huang and Chao-Cheng Lee},
year = {2013},
doi = {10.1109/JSSC.2013.2237991},
url = {http://dx.doi.org/10.1109/JSSC.2013.2237991},
researchr = {https://researchr.org/publication/LeePCWCLWTHL13},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {48},
number = {4},
pages = {1018-1030},
}