Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming - researchr publication

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Tun Li, Yang Guo, Gongjie Liu, Sikun Li. Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. In Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal. pages 17-25, IEEE Computer Society, 2005. [doi]

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