A compact low-power VLSI architecture for real-time sleep stage classification - researchr publication authors

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Peter Zhi Xuan Li, Hossein Kassiri, Roman Genov. A compact low-power VLSI architecture for real-time sleep stage classification. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016. pages 1314-1317, IEEE, 2016. [doi]

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