The following publications are possibly variants of this publication:
- Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmabilityYan Lin, Fei Li, Lei He. fpga 2005: 199-207 [doi]
- A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan. fpga 2011: 281 [doi]
- Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabricsFei Li, Yan Lin, Lei He, Jason Cong. fpga 2004: 42-50 [doi]