The following publications are possibly variants of this publication:
- A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data RecoveryChih-Fan Liao, Shen-Iuan Liu. jssc, 43(11):2492-2502, 2008. [doi]
- A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDRChih-Fan Liao, Shen-Iuan Liu. isscc 2008: 100-101 [doi]
- Design of a 25-Gb/s PAM-4 VCSEL Diode Driver with an Equalizer in 90-nm CMOS TechnologyTsung-Yen Wu, Jau-Ji Jou, Tien-Tsorng Shih, Po-Jui Chiang, Yaw-Dung Wu. iscas 2019: 1-4 [doi]
- A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link ReceiversJian-Hao Lu, Shen-Iuan Liu. jssc, 45(2):433-446, 2010. [doi]