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An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS

Ziyu Li, Weiwei Shan, Chengjun Wu, Haitao Ge, Jun Yang 0006. An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, November 7-10, 2021. pages 1-3, IEEE, 2021. [doi]

Authors

Ziyu Li

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Weiwei Shan

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Chengjun Wu

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Haitao Ge

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Jun Yang 0006

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