The following publications are possibly variants of this publication:
- A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data RecoveryChih-Fan Liao, Shen-Iuan Liu. jssc, 43(11):2492-2502, 2008. [doi]
- A PAM-4 adaptive analog equalizer with decoupling control loops for 25-Gb/s CMOS serial-link receiverShunbin Li, Peng Liu, Weidong Wang, Xing Fang, Dong Wu, Xiang-Hui Xie. socc 2015: 221-226 [doi]
- A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link ReceiversJian-Hao Lu, Shen-Iuan Liu. jssc, 45(2):433-446, 2010. [doi]