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True hardware random number generation implemented in the 32-nm SOI POWER7+ processor

John S. Liberty, Adrian Barrera, David W. Boerstler, Thomas B. Chadwick, Scott R. Cottier, H. Peter Hofstee, Julie A. Rosser, Marty L. Tsai. True hardware random number generation implemented in the 32-nm SOI POWER7+ processor. IBM Journal of Research and Development, 57(6), 2013. [doi]

Authors

John S. Liberty

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Adrian Barrera

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David W. Boerstler

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Thomas B. Chadwick

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Scott R. Cottier

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H. Peter Hofstee

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Julie A. Rosser

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Marty L. Tsai

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