The following publications are possibly variants of this publication:
- An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode DesignsKyoung-Hwan Lim, Deokjin Joo, Taewhan Kim. tcad, 32(3):392-405, 2013. [doi]
- Useful clock skew scheduling using adjustable delay buffers in multi-power mode designsJuyeon Kim, Taewhan Kim. aspdac 2015: 466-471 [doi]
- Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designsKitae Park, Geunho Kim, Taewhan Kim. date 2014: 1-4 [doi]
- Adjustable Delay Buffer Allocation under Useful Clock Skew SchedulingJuyeon Kim, Taewhan Kim. tcad, 36(4):641-654, 2017. [doi]
- Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modesJuyeon Kim, Deokjin Joo, Taewhan Kim. integration, 52:91-101, 2016. [doi]
- An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problemJuyeon Kim, Deokjin Joo, Taewhan Kim. dac 2013: 90 [doi]