Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction

Yan Lin, Lei He. Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(10):2023-2034, 2006. [doi]

Abstract

Abstract is missing.