The following publications are possibly variants of this publication:
- Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reductionYan Lin, Lei He. dac 2005: 720-725 [doi]
- An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reductionYan Lin, Yu Hu, Lei He, Vijay Raghunat. islped 2006: 168-173 [doi]
- Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reductionYu Hu, Yan Lin, Lei He, Tim Tuan. dac 2006: 478-483 [doi]
- A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan. fpga 2011: 281 [doi]
- Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reductionYan Lin, Lei He. date 2007: 636-641 [doi]
- Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retimingYu Hu, Yan Lin, Lei He, Tim Tuan. todaes, 13(2), 2008. [doi]
- Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabricsFei Li, Yan Lin, Lei He, Jason Cong. fpga 2004: 42-50 [doi]
- FPGA power reduction using configurable dual-VddFei Li, Yan Lin, Lei He. dac 2004: 735-740 [doi]