Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi. Soft-Error Hardening Designs of Nanoscale CMOS Latches. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA. pages 41-46, IEEE Computer Society, 2009. [doi]
@inproceedings{LinKL09-0,
title = {Soft-Error Hardening Designs of Nanoscale CMOS Latches},
author = {Sheng Lin and Yong-Bin Kim and Fabrizio Lombardi},
year = {2009},
doi = {10.1109/VTS.2009.10},
url = {http://dx.doi.org/10.1109/VTS.2009.10},
researchr = {https://researchr.org/publication/LinKL09-0},
cites = {0},
citedby = {0},
pages = {41-46},
booktitle = {27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA},
publisher = {IEEE Computer Society},
isbn = {978-0-7695-3598-2},
}