Soft-Error Hardening Designs of Nanoscale CMOS Latches

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi. Soft-Error Hardening Designs of Nanoscale CMOS Latches. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA. pages 41-46, IEEE Computer Society, 2009. [doi]

Abstract

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