A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi. A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors. IEEE Trans. VLSI Syst., 19(5):900-904, 2011. [doi]

@article{LinKL11,
  title = {A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors},
  author = {Sheng Lin and Yong-Bin Kim and Fabrizio Lombardi},
  year = {2011},
  doi = {10.1109/TVLSI.2010.2043271},
  url = {http://dx.doi.org/10.1109/TVLSI.2010.2043271},
  researchr = {https://researchr.org/publication/LinKL11},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {19},
  number = {5},
  pages = {900-904},
}