SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits - researchr publication authors

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Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh. SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits. In Tony Ambler, Jochen A. G. Jess, Hugo De Man, editors, Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991. pages 142-148, EEE Computer Society, 1991. [doi]

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