Transistor-level layout of high-density regular circuits

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly. Transistor-level layout of high-density regular circuits. In Gi-Joon Nam, Prashant Saxena, editors, Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009. pages 83-90, ACM, 2009. [doi]

Abstract

Abstract is missing.