Layout Generator for Transistor-Level High-Density Regular Circuits

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly. Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(2):197-210, 2010. [doi]

Authors

Yi-Wei Lin

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Malgorzata Marek-Sadowska

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Wojciech Maly

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