Layout Generator for Transistor-Level High-Density Regular Circuits

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly. Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(2):197-210, 2010. [doi]

@article{LinMM10,
  title = {Layout Generator for Transistor-Level High-Density Regular Circuits},
  author = {Yi-Wei Lin and Malgorzata Marek-Sadowska and Wojciech Maly},
  year = {2010},
  doi = {10.1109/TCAD.2009.2035580},
  url = {http://dx.doi.org/10.1109/TCAD.2009.2035580},
  tags = {layout},
  researchr = {https://researchr.org/publication/LinMM10},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {29},
  number = {2},
  pages = {197-210},
}