An Efficient VLSI Architecture for Nonbinary LDPC Decoders - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Jun Lin, Jin Sha, Zhongfeng Wang, Li Li 0003. An Efficient VLSI Architecture for Nonbinary LDPC Decoders. IEEE Trans. on Circuits and Systems, 57-II(1):51-55, 2010. [doi]

The following publications are possibly variants of this publication:

An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum AlgorithmChia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee. tcas, 63-II(9):863-867, 2016. [doi]

Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC CodesJun Lin, Zhiyuan Yan. tvlsi, 21(9):1756-1761, 2013. [doi]

An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC CodesJun Lin, Zhiyuan Yan. tvlsi, 22(12):2649-2660, 2014. [doi]

Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC CodesXiaoheng Chen, Shu Lin, Venkatesh Akella. tcas, 59-I(1):188-197, 2012. [doi]

runs on WebDSL