Chun-Yu Lin, Tun-Ju Wang, Tsung-Hsien Lin. A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. pages 253-256, IEEE, 2017. [doi]
@inproceedings{LinWL17-7,
title = {A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS},
author = {Chun-Yu Lin and Tun-Ju Wang and Tsung-Hsien Lin},
year = {2017},
doi = {10.1109/ASSCC.2017.8240264},
url = {https://doi.org/10.1109/ASSCC.2017.8240264},
researchr = {https://researchr.org/publication/LinWL17-7},
cites = {0},
citedby = {0},
pages = {253-256},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017},
publisher = {IEEE},
isbn = {978-1-5386-3178-2},
}