The following publications are possibly variants of this publication:
- 2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converterTae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park. isscc 2013: 254-255 [doi]
- A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase DetectorWei-Sung Chang, Po-Chun Huang, Tai-Cheng Lee. jssc, 49(12):2964-2975, 2014. [doi]
- Fractional spur suppression in all-digital phase-locked loopsPeng Chen, Xiongchuan Huang, Robert Bogdan Staszewski. iscas 2015: 2565-2568 [doi]
- A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase NoiseYing Wu, Mina Shahmohammadi, Yue Chen, Ping Lu, Robert Bogdan Staszewski. jssc, 52(7):1885-1903, 2017. [doi]