A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. J. Solid-State Circuits, 40(5):1047-1056, 2005. [doi]

Authors

Hung-Chih Liu

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Zwei-Mei Lee

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Jieh-Tsorng Wu

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