The following publications are possibly variants of this publication:
- Correction to "A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration"Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu. jssc, 40(11):2339, 2005. [doi]
- A digital background calibration technique for pipelined analog-to-digital convertersHung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu. iscas 2003: 881-884 [doi]
- A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital ConverterChi-Chang Lu, Tsung-Sum Lee. tcas, 54-II(8):658-662, 2007. [doi]
- A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital ConverterChi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee. iscas 2007: 1955-1958 [doi]