Chieh-Pu Lo, Wen-Zhang Lin, Wei-Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya-Chin King, Chrong Jung Lin, Yu-Der Chih, Tsung-Yung Jonathon Chang, Meng-Fan Chang. A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation. J. Solid-State Circuits, 54(2):584-595, 2019. [doi]
@article{LoLLLYCKLCCC19,
title = {A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation},
author = {Chieh-Pu Lo and Wen-Zhang Lin and Wei-Yu Lin and Huan-Ting Lin and Tzu-Hsien Yang and Yen-Ning Chiang and Ya-Chin King and Chrong Jung Lin and Yu-Der Chih and Tsung-Yung Jonathon Chang and Meng-Fan Chang},
year = {2019},
doi = {10.1109/JSSC.2018.2873588},
url = {https://doi.org/10.1109/JSSC.2018.2873588},
researchr = {https://researchr.org/publication/LoLLLYCKLCCC19},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {54},
number = {2},
pages = {584-595},
}