Atieh Lotfi, Abbas Rahimi, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, Rajesh K. Gupta. Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration. In Luca Fanucci, Jürgen Teich, editors, 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016. pages 1279-1284, IEEE, 2016. [doi]
@inproceedings{LotfiRYEG16,
title = {Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration},
author = {Atieh Lotfi and Abbas Rahimi and Amir Yazdanbakhsh and Hadi Esmaeilzadeh and Rajesh K. Gupta},
year = {2016},
url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=7459507},
researchr = {https://researchr.org/publication/LotfiRYEG16},
cites = {0},
citedby = {0},
pages = {1279-1284},
booktitle = {2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016},
editor = {Luca Fanucci and Jürgen Teich},
publisher = {IEEE},
isbn = {978-3-9815-3707-9},
}