A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology - researchr publication authors

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Amr Lotfy, Syed Feruz Syed Farooq, Qi S. Wang, Soner Yaldiz, Praveen Mosalikanti, Nasser A. Kurd. A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. In 2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015. pages 1-4, IEEE, 2015. [doi]

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