Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS

Yue Lu, Elad Alon. Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS. J. Solid-State Circuits, 48(12):3243-3257, 2013. [doi]

@article{LuA13-2,
  title = {Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS},
  author = {Yue Lu and Elad Alon},
  year = {2013},
  doi = {10.1109/JSSC.2013.2278804},
  url = {http://dx.doi.org/10.1109/JSSC.2013.2278804},
  researchr = {https://researchr.org/publication/LuA13-2},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {48},
  number = {12},
  pages = {3243-3257},
}