Testing 3D chips containing through-silicon vias

Erik Jan Marinissen, Yervant Zorian. Testing 3D chips containing through-silicon vias. In Gordon W. Roberts, Bill Eklow, editors, 2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009. pages 1-11, IEEE, 2009. [doi]

Authors

Erik Jan Marinissen

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Yervant Zorian

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