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Erik Jan Marinissen, Yervant Zorian. Testing 3D chips containing through-silicon vias. In Gordon W. Roberts, Bill Eklow, editors, 2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009. pages 1-11, IEEE, 2009. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Testing 3D Stacked ICs Containing Through-Silicon ViasErik Jan Marinissen. In Abbas Sheibanyrad, Frédéric Pétrot, Axel Jantsch, editors, 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems, pages 47-74, Springer, 2011. [doi]
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