Erik Jan Marinissen, Yervant Zorian. Testing 3D chips containing through-silicon vias. In Gordon W. Roberts, Bill Eklow, editors, 2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009. pages 1-11, IEEE, 2009. [doi]
@inproceedings{MarinissenZ09-0,
title = {Testing 3D chips containing through-silicon vias},
author = {Erik Jan Marinissen and Yervant Zorian},
year = {2009},
doi = {10.1109/TEST.2009.5355573},
url = {http://dx.doi.org/10.1109/TEST.2009.5355573},
researchr = {https://researchr.org/publication/MarinissenZ09-0},
cites = {0},
citedby = {0},
pages = {1-11},
booktitle = {2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009},
editor = {Gordon W. Roberts and Bill Eklow},
publisher = {IEEE},
isbn = {978-1-4244-4868-5},
}